top of page
Tern Systems Logo (with text)(with slogan)(transparent background).png
Image by Sergey Zolkin

TERN

The most powerful microprocessor instruction set architecture to date

Ternary Executable Ratiocinative Nexus (TERN) is an assembler programming language built to take full advantage of BTMC-compliant machines

Image by Pawel Czerwinski

125 total instruction
64 base instructions
61 pseudo-instructions

Three-way branching
Middle moves
Large model sizes

We have laid the groundwork for you to take control and harness the full potential of the ternary microprocessor

Image by Sebastian Svenson

Three-way branching
Middle moves
Large model sizes

Image by Andrew Kliatskyi

.modl sm

.section .data

.wrd a 100

.wrd b 2000

.wrd c 1000

.wrd res 0t0

.section .txt

main:

lwl t1, b

push t2

move t2, t1

...

We know new can be scary...

...that's why we based TERN off RISC-V

Image by Andrew Kliatskyi

...

lwl t1, a

bg t1, t2, set_resreg_6

add t1, zero, 0t0

jal x0, exit_bg_6

set_resreg_6:

addi t1, zero, 0t+

exit_bg_6:

pop t2

be t1, zero, else_15

...

Image by Adam Le Sommer

Build Anew

All Ways

bottom of page